1. Field of the Invention
The present invention generally relates to electrical interfaces with input/output (I/O) ports of circuits implemented in an integrated circuit (IC) chip and, more particularly, to a technique for reducing the number of pins required for electrical interfaces to and from a chip while still maintaining the number of I/O ports for the chip.
2. Background Description
The number of pins is a primary factor in determining the physical dimensions of the chip and the number of I/O ports which may be accommodated. Many chips are I/O limited; that is, there are more I/O ports than there are available pins, given a certain maximum chip size. In order to fit on the smallest chip size possible, and be cost competitive, some way of reducing the number of pins required for chip I/Os is needed.
One technique known in the prior art for minimizing the number of pins yet providing the required interconnections to the chip I/Os is to multiplex a limited number of pins. Using this technique, a limited number of pins are used for interfacing to a greater number of I/O ports within the chip. One or more pins are used to input a selection code to a multiplexer/demultiplexer on the chip which routes connections between the I/O ports and the pins according to the selection code. This approach, however, while limiting the number of pins has several drawbacks. First, the on-chip multiplexer/demultiplexer requires a considerable amount of valuable chip real estate and can be quite complex, adding to the cost of the chip. Second, the process of multiplexing and demultiplexing slows data through put, degrading performance of the chip.
There are some chips having specialized functions that require fast data through put but need to be made as small and inexpensively as possible, including limiting the number of pins for the chip. One such chip is a parallel to serial converter. What is needed is a way to minimize the number of pins without adversely affecting the data through put and the necessity of a complex multiplexer/demultiplexer on the chip.